By Larry E. Mosley; Intel Corporation Santa Clara, CA 95054 USA
PASSIVE COMPONENT INDUSTRY MAY/JUNE 2006
Microprocessor power levels in the past have increased exponentially1, which has led to increased complexity and cost of both power delivery and power removal. In particular, it has led to a need to exponentially lower the impedance of decoupling capacitors (lower inductance and resistance and higher capacitance). In light of this need, there has been a drive to cap the power levels or at least to significantly slow their growth. However, this does not necessarily mean that we won’t need to continue to improve the performance of the capacitors in the future. In the first part of this paper we will discuss the use of capacitors for decoupling microprocessors and will look into our crystal ball and try to predict what improvements in impedance may be needed. Along with these improvements is the need to better understand just what is the impedance of the capacitors. This is true especially in the case of MLCCs where, because of the nonlinear nature of the dielectric materials, the amount of capacitance available under use conditions may be very different from what is on the label. So, in the second part of the paper we will discuss some of the issues associated with measuring the capacitance of non-linear dielectric materials and some of the design implications; we will also call for improvement in how the amount of capacitance is specified.
Part 1: Capacitors in Microprocessor Power Delivery:
Figure 1a shows a simplified circuit diagram from the voltage regulator to the microprocessor. In a typical system the microprocessor switching speed is much greater than that of the voltage regulator; for example, a desktop system may have a 3GHz microprocessor with a 300kHz voltage regulator. In this example the microprocessor switching speed is 10,000 times faster than that of the voltage regulator. When there is a sudden increase in switching current from the microprocessor (Figure 1b) the voltage regulator cannot respond as fast, so capacitors are used to act as temporary sources of power until the voltage regulator can ramp up its output current to the new level demanded by the microprocessor. The choice of capacitors depends on many factors including cost, available space, and how much of a voltage droop can be tolerated. In balancing these factors, several stages of capacitors are used, as shown in Figure 2, which includes available options; however, it is unlikely that all of these options would be implemented in a single design. In practice, one typically has low inductance, low capacitance capacitors close to the die (and could include capacitance on the die itself), with capacitors on the top or bottom side of the package substrate, or embedded in the package. As one moves away from the die and closer to the voltage regulator, the inductance and the capacitance of the capacitors both increase. On the package or interposer, if one is used, there could be larger capacitors to provide extra charge storage not available in the low inductance capacitors. On the motherboard are the bulk capacitors which provide the bulk of the charge required by the microprocessor until the voltage regulator can start supplying the current; they also filter the output voltage from the voltage regulator.
In the example shown in Figure 1a, four stages of decoupling are used, the first of which is capacitance on the die itself (Cdie), capacitance that is either added to the die or is inherent to the chip itself. The other three stages are on the package and/or motherboard, with each stage having more capacitance than the previous stage, but also with a higher inductance. Figure 1c shows the voltage response as measured at the die as a result of a sudden increase in the current. In the ideal case, with each stage having matched impedance, the response would be flat. However, matching the impedance of each stage is difficult to do in practice, so instead the response shows voltage oscillations as each stage of decoupling responds. Note in the figure that the time scales are logarithmic.
The magnitude and duration of the voltage droops depend on the stimulus, current waveform, as shown in Figure 1b, and the impedance (Z) of each stage of decoupling:
Z = R + j(ωL – 1/ωC)
where R, L, and C are respectively the resistance, inductance, and capacitance, and ω is the angular frequency. During a current transient a capacitor goes through essentially 3 phases: inductive, where the voltage drop is dominated by L(di/dt), di/dt being how fast the current (i) changes; a resistive iR drop, which includes the resistance of the capacitor (ESR) and the interconnect; and capacitive Q/C, which is a measure of how much charge (Q) has been removed from the capacitor. The voltage droop from the first loop, labeled as L1 in Figure 1, is dominated by the amount of capacitance on the die (Cdie) and the inductance between Cdie and the first stage of capacitance on the package (C1) and includes the inductance (ESL) of the capacitor (C1) itself and the interconnect inductance to the die. The resistance in this loop is fairly low and to good approximation the impedance of this loop is:
Z ~ (L/Cdie)1/2
Note that the capacitance in Equation 2 is just that of the die. While this is not strictly true, in practice the capacitance of C1 is chosen to be much larger than Cdie (>10x), which makes this a good approximation. At the other extreme are the loops labeled L3 and L4 in Figure 1a. The loop L4 depends primarily on the switching speed and bandwidth of the voltage regulator and will not be discussed here. As previously mentioned, capacitor C3, which forms part of Loop L3, serves two purposes: one is to filter the output voltage from the voltage regulator, and the other is to provide the majority of the charge to the microprocessor during a transient current event. While the inductance of these capacitors cannot be ignored, the dominant factors are the ESR of these capacitors and the magnitude of the capacitance. During the phase in which C3 is supplying current, the iR drop includes the ESR of the capacitor and that of the interconnect. Since these capacitors are typically on the motherboard, the interconnect resistance (including motherboard, socket, and package) can be large enough that when coupled with the high currents seen today, can lead to a substantial iR drop. In the final phase, when the voltage regulator begins to supply the total current, the voltage drop is approximated by:
V ~ iR + Q/C
where C is the total capacitance but is dominated by C3. Since the iR drop can be quite large, C3 needs to be fairly large to minimize the voltage droop. Finally, a few words in reference to loop 2 (L2). In Figure 1 there are three levels of capacitance (C1, C2, and C3); however, as an example, a recent design used four stages of capacitors. On the package were two stages of Multi-Layer Ceramic Capacitors (MLCC); a significant number of 8-terminal capacitors on the land side of the package to minimize the inductance, and a few 2-terminal capacitors to increase the amount of capacitance. On the motherboard were two more stages: a mixture of aluminum polymer capacitors for bulk capacitance and a large number of 2-terminal MLCCs to reduce the effective resistance. The capacitors in loop 2 fill these intermediate C and R requirements and are important, but are not the major drivers for improved capacitor technology. As should be quite evident, such a design uses a lot of capacitors and real estate, which both drive up the cost of power delivery.
Impedance Trends: Past and Future
As mentioned in the last section, the magnitude of the voltage droop depends on the current and impedance. In this section we will discuss impedance design targets and trends. As part of this we will look at the historic trends in impedance and try to project them out into the future and discuss the implications for the impedance of each capacitance stage, especially for the first and last stages. The total impedance of the system includes the die itself (Zd) and the power delivery system (Zs) from the voltage regulator to the die. As an example, if the output voltage from the regulator is to be 1V and the processor current is 100A then the total impedance should be about 10mohms:
Z = Zd + Zs = V/i = 1V/100A = 10mohms
In order to determine what the system impedance needs to be, we need to decide what voltage droop or noise margin can be tolerated at the die; the larger the voltage droop the lower the voltage at the transistor, and therefore the slower the transistor switches. In a higher end system a 10% droop is typically targeted, or 100mV in our example. Our target impedance for this system would then be 1mohms:
Zs = Vs/i = 100mV/100A = 1mohm
Figure 3 shows the impedance trend over time; the solid line is based on historical data. Although the rate of decrease of the impedance has slowed over the years, it is still declining. Projecting these trends into the future is difficult since there are a number of unknowns. As previously mentioned, the high power levels and cost of power delivery has led to a push to cap the power or at least to significantly reduce the rate of increase. How successful this is will have a large impact on the impedance needs. Even if the power is capped, there is still a trend to lower voltages, which will continue to drive the need for lower impedances. Consider if we had a 100W processor at 1.25V, the current would be 80A and the impedance target, assuming a 10% noise margin, would be about 1.6mohm. If the power remained the same but the voltage dropped to 1V, the current would increase to 100A and, assuming the same 10% noise margin, the impedance target would drop to 1mohm. So even if we were to cap the power we would still need lower impedance capacitors. Leakage current has also been increasing, and while this is more of a resistive drop, it eats into our noise margins and also impacts the needed impedance.
Finally, cost factors may become prohibitive if too low an impedance is needed, and may lead to a relaxation of the noise margins, but this would come with a performance penalty. Taking all these factors into account, we have tried to provide a range of values, which hopefully, covers the range over the next several years. The dotted (upper) line in Figure 3 assumes about a 20% impedance reduction per process generation, approximately every two years, and the dashed (lower) line is a 30% reduction per year. Based on this, over the next six years we could expect that the impedance would need to be reduced between 50-70% of what it is today. Next, we’ll take a look at what this may mean for capacitor technology, in particular for the first and last stages described in Figure 1. As Equation 2 shows, the impedance of the first stage depends primarily on the amount of capacitance on the die and the loop inductance from the first capacitor stage to the die, and includes the ESL of C1 and the interconnect inductance. The amount of capacitance on die is not expected to change very much in the near future, which means that any impedance reduction will most likely need to come from the inductance. Since the impedance is proportional to the square root of the inductance a 50-70% reduction in impedance will mean a 70-90% reduction in inductance. Currently the interconnect inductance accounts for about 1/3 of the total inductance, which means that even if we had zero inductance, capacitors would still not meet our targets unless the interconnect inductance is also reduced. It probably doesn’t make sense to drive to lower inductance capacitors if the interconnect inductance is much more than half of the total. Assuming a 50-50 split between package and capacitor inductance means the capacitor inductance would need to reduce by about 80-90%.This also means that the package inductance would need to reduce by 50-85%, which will be challenging given that the package inductance has not historically scaled with that of the capacitors. It should be noted that the capacitor inductance
referred to here is the effective inductance, so that in the case of using a number (N) of capacitors in parallel it is Lc/N, where Lc is the inductance per capacitor. In addition to lowering the inductance of the capacitor, one could use smaller capacitors of less than or equal inductance and increase the total number in the same area, and also reduce the effective inductance. At the other extreme we could make the interconnect inductance negligibly small so that the capacitor inductance would need to reduce by 45-85%; this would require significant changes to the packaging technology.
The needed reduction in inductance discussed above covers quite a wide range and contains a lot of uncertainty, but one thing seems clear: we will need significant reductions in both the capacitor and the package. There are many ways to tackle this problem, from improving existing technology to dramatic new technologies; however the final solution will most likely be that which is most cost effective.
For the first loop in Figure 1a, the key factor is low inductance; on the motherboard it is low ESR and high capacitance (C3). As with the package inductance, the resistance of the system (package, socket, and motherboard) has improved over the years—but not nearly fast enough to keep up with the impedance targets.
This has put a lot of pressure on the capacitors to take up the slack. As previously discussed, a recent design had two stages of capacitors on the motherboard, a number of MLCCs to lower the resistance, and a number of aluminum polymers to increase the bulk capacitance. At present the majority of the resistance is in the interconnect, so this will have to reduce faster in the future than it has in the past. Assuming the same ratio of interconnect to capacitor resistance means we will need the ESR to decrease in the 50-70% range in order to match the impedance trends. For a given capacitor form factor, such as 1206, the inductance does not change with capacitance, so in order to meet the 50-70% impedance reduction targets, the capacitance will need to increase in the range of 350-1000%. There will probably also be a need to reduce the inductance of C3, which may mean using smaller form factor capacitors with lower inductance and more in parallel. For example, in order to reduce the inductance we could use 0805s in place of 1206s: lower inductance and more capacitors in the same area. However, with this strategy we would lose capacitance density. For reasons such as this, there may be a need for an additional 4x increase in capacitance density, meaning a 1400- 4000% total increase in capacitance density.
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